The present invention relates to a fabrication method of flash memory device and, more particularly, to a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer and use the poly spacer as a floating gate.
Flash memories are nonvolatile memories utilizing floating gate transistors as the basis. A flash memory arranges memory cells in arrays in a way suitable to its own operation. The memory cell is generally used to store a single bit of data.
In a conventional fabrication process of flash memory, a spacer structure is first fabricated on a semiconductor substrate. The spacer structure is then used to define the channel length. However, in this method, control of profile of the spacer is difficult, and the implanted positions of source and drain cannot be accurately controlled. Therefore, it is difficult to control the channel length.
Besides, in the present flash memory techniques, the spacer can be used as the floating gate. For instance, U.S. Pat. No. 5,427,968 disclosed a method for fabricating a split-gate flash memory cell with separated and self-aligned tunneling regions. Referring to FIG. 1, a semiconductor substrate 30 is provided with a gate oxide 32 and a silicon nitride 34 formed on the surface thereof, as shown in FIG. 1(a). The silicon nitride 34 is etched out by means of photolithography, and the exposed gate oxide 32 is removed. A tunnel oxide 36 and a floating gate 38 are formed in order on the substrate 30. A floating gate 38 of annular poly spacer structure is formed to enclose the silicon nitride 34 by means of anisotropic etch, as shown in FIG. 1(b). A source 40 and a drain 42 are formed in the semiconductor substrate 30 by means of ion implantation. The silicon nitride 34 is then removed. Next, an insulating dielectric 44 as shown in FIG. 1(c) is formed on the floating gate 38 and the surface of the exposed substrate 30. Subsequently, a poly silicon is deposited on the surface of the insulating dielectric 44. The poly silicon is then etched to form a control gate 46, as shown in FIG. 1(d). A flash memory cell structure is thus formed.
However, in the above method, it is difficult to control the profile and length of the spacer because of slight difference of fabrication parameters and devices when the spacer is fabricated so that it is difficult to control the channel length of memory. Moreover, the channel lengths of flash memories fabricated at different times are inconsistent so that repetitive control cannot be achieved.
Additionally, the.operation of the flash memory depends on the technique of injecting or removing charges of the floating gate. When erasing data, this kind of floating gate of poly spacer needs tips to perform point discharge so that charges can be removed by means of the Fowler-Nordheim tunneling effect. In this U.S. patent, the fabricated floating gate of poly spacer has no good tip structure so that the effect of point discharge is limited when erasing data.
Accordingly, the present invention aims to propose a fabrication method used to fabricate a poly spacer and devices like flash memory cells so as to resolve the drawbacks in the prior art.
The primary object of the present invention is to propose a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer and use the poly spacer as a floating gate so as to obtain a channel length of stability and easy control and tips useful for point discharge. Repetitive control of fabrication of semiconductor devices can thus be achieved.
Another object of the present invention is to propose a method for fabricating semiconductor devices having good profiles.
To achieve the above objects, an oxide and a predefined and patterned first dielectric are formed on the surface of a semiconductor substrate. A first poly silicon and a second dielectric are then formed in order on the surfaces of the oxide and the first dielectric. Next, anisotropic etch is performed to the second dielectric to form dielectric spacer around the first poly silicon. The first poly silicon is then etched with the dielectric spacer as a mask. To form poly spacer around the first dielectric. Finally, the first dielectric is removed. A poly spacer structure is thus completed.
Ion doped regions used as a source and a drain are formed in the semiconductor substrate by using the above poly spacer already formed on the semiconductor substrate. An insulating dielectric and a control gate are formed in order on the semiconductor substrate. A flash memory structure using the poly spacer as a floating gate is thus formed.